• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    The invention relates to the production of spacers (230) at flanks (206, 207) of a transistor gate (200), comprising a step of forming a dielectric layer (231) covering the gate (200) and a peripheral zone (220, 221) of a layer of semiconductor material (212) surrounding the gate (200) comprising the following steps: - formation of a surface layer (232) covering the grid (200) and the peripheral zone ; partial removal of the surface layer (232) configured to completely remove the surface layer (232) at the peripheral area (220, 221) while preserving a residual portion (234) of the surface layer (232) at the flanks (206,207); selective etching of the dielectric layer (231) with respect to the material of the residual portion (234) of the surface layer (232) and with respect to the semiconductor material (212).
    公开号:FR3025938A1
    申请号:FR1458759
    申请日:2014-09-17
    公开日:2016-03-18
    发明作者:Christian Arvet；Sebastien Barnola；Sebastien Lagrasta；Nicolas Posseme
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics SA；STMicroelectronics Crolles 2 SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD OF THE INVENTION The present invention relates to transistors, particularly transistors of the MOS type (Metal Oxide Semiconductor) and more particularly to the realization of gate spacers of such transistors.
    [0002] The microelectronics industry, understood here as including nanotechnology, is concerned with the invention, in the use of field effect transistors and in particular MOSFET transistors widely used in integrated circuits.
    [0003] STATE OF THE ART An example of a technique for producing the source and drain zones of such transistors is given by the publication WO-A1-0229881. This document also shows a case of manufacturing grid spacers. Figure 1 is a sectional view of an example of this type of transistor in progress. It contains the source and drain zones 120, 121. The grid 100 conventionally consists of a stack of layers, a large part of which is still made of polycrystalline silicon 101. The formation of the source and drain zones 120, 121 is typically by ion implantation of dopants in the zones 120, 121, the gate 100 serving as a mask as mentioned above, thus preventing doping of the area of the transistor in which, depending on the voltages applied to the gate 100, will be able to develop the conduction channel 105 between source and drain. The basic technique, very briefly described above, has been constantly improved in order to improve the electrical performance of the transistors while allowing to accommodate the successive size reductions of the transistors required by an ever increasing integration of a more large number of components in an integrated circuit. One technique currently used consists in manufacturing the integrated circuits starting from elaborate silicon-on-insulator substrates, designated by their acronym SOI, of the English "silicon on insulator". The SOI-developed substrate is characterized by the presence of a thin surface layer of monocrystalline silicon, of Germanium or of silicon-germanium 112 resting on a continuous insulating layer of oxide 111, in particular of silicon, called buried oxide 302 593 8 2 or still BOX acronym for "buried oxide layer". The layer 111 rests on the layer 110 which constitutes the body of the SOI substrate, often called the English word "bulk" to indicate that the starting substrate is very generally made of solid silicon. This structure offers many advantages for the realization of MOSFET transistors. In particular, it allows a drastic reduction of parasitic capacitances due to the presence of the insulating continuous layer 111. The layers 103 and 104 constitute the gate oxide comprising most often in recent embodiments a layer 104 of a high-grade material. relative permittivity called "high-k". Layer 102 is a hard mask for protecting, at this stage, the stack of underlying gate layers. The surface layer 112, for example made of monocrystalline silicon, can be precisely controlled in terms of thickness and doping. In particular, it is advantageous for the performance of the transistors that the channel 105 can be completely deserted from carriers, that is to say "fully depleted" (FD), an English term that is generally used to designate this state. This is achieved by making the transistors from SOI substrates whose surface layer 112 is very thin. This type of transistor is thus designated by the acronym FDSOI. An improvement in the basic self-alignment technique that has been universally adopted is the formation of spacers 130 on the flanks of the grid 100. The spacers 130, typically made of silicon nitride (SiN), will enable in particular the implementation of a so-called "raised source and drain" technique, an intermediate result of which is visible in FIG. 4. It has become commonplace for these operations to be performed twice in succession in order to obtain the result final which is illustrated in Figure 7 where one can distinguish two levels of spacers and the two corresponding levels of elevation of the source and drain zones. In order to maintain low electrical resistance to access the source and drain electrodes, despite the size reduction of the transistors, it was indeed necessary to increase their section. This is obtained by selective epitaxy of the source / drain zones 120, 121. During this operation, the initial surface layer 112 of monocrystalline silicon will be grown locally. It is then necessary to protect the grid areas to prevent growth from also occurring from the polycrystalline silicon of the grid. It is, among other things, the role of spacers to ensure this function. They also perform a role of preserving the gate during siliciding of the contacts (not shown) which is then performed for the same purpose in order to reduce the series resistance of access to the electrodes of the transistor. The formation of the spacers 130 has become a crucial step in the formation of transistors that now reach dimensions that are commonly measured in nanometers (nm = 10-9 meters) and which are generally of decananometric sizes. The production of spacers 130 is done in this technology without involving any photoengraving operation. To achieve this, FIG. 2 shows the formation of a first nitride layer 131, in particular silicon nitride (salt). This layer is then subjected, in the step of FIG. 3, to a strongly anisotropic etching so that the etching removes the portions of the layer 131 situated on the surface layer 112 (which are generally horizontal, ie ie oriented perpendicularly to the thickness of the substrate 110) while preserving, at least in part, the nitride on the non-horizontal parts and particularly on the parts forming the sidewalls (106, 107 of the grid 100).
    [0004] A first level of spacers constituted by the residual parts made of nitride covering the flanks 106, 107 is thus obtained. After a wet cleaning, the first step of growth of the sources and drains is carried out, as in FIG. by epitaxy at zones 120, 121.
    [0005] Second level spacers are then produced. For this purpose, a new layer of nitride 132 is deposited, as shown in FIG. 5. Similarly to the case of FIG. 3, FIG. 6 illustrates an etching of the nitride layer 132 such that the layer 132 is not preserved, at least in part, only on the flanks of the grid, covering the spacers already formed at this level. Overall, these steps lead to spacers whose foot has a withdrawal.
    [0006] A new phase of epitaxy is then produced so that the source / drain zones 120, 121 grow around the grid 100, the latter being protected by the spacers 130 as shown in FIG. 7. The technology thus described is reveals complex, especially by the number of steps implemented. In general, and even for the production of single-level spacers, the current techniques do not make it possible to precisely control the etching phases and thus the final shape of the constituent parts of the transistor, in particular the shape of the base of the spacers.
    [0007] The present invention addresses at least some of the disadvantages of present techniques. SUMMARY OF THE INVENTION One aspect of the invention relates to a method of making spacers at flanks of a transistor gate in which the gate is located above a layer of semi-solid material. -driver. Advantageously, the method successively comprises the following steps: - formation of a dielectric layer which covers the gate and at least one peripheral zone of the layer of semiconductor material 20 surrounding the gate; - formation of a surface layer covering the dielectric layer; partial etching of the superficial layer configured to completely remove the surface layer at the peripheral zone while preserving a residual portion of the surface layer at the sidewalls; etching the dielectric layer selectively with respect to the residual part of the surface layer and with respect to the layer of semiconductor material. Thus, during the etching step of removing material from the dielectric layer above the areas around the gate (i.e. at the source / drain areas), the portion of this layer, which is at the level of the grid flanks, is protected by the superficial layer remaining at this point. The parameters of the final etching, which is a selective etching relative to the surface layer, can thus be more freely adjusted, so as to control, for example, the shape to be given to the stand of the spacers, or else to avoid an attack of the material of the surface layer, for example nanocrystalline silicon (but possibly also germanium or silicon-germanium). According to one embodiment, the formation of the surface layer comprises a modification of the material of only a portion of the thickness of the dielectric layer. It is therefore not necessarily required to perform a deposition step to achieve the surface layer. In particular, the material of the dielectric layer can be oxidized, particularly if it is based on or made of nitride, such as silicon nitride. In this regard, it should be noted that the oxidation can be performed by plasma under isotropic or quasi-isotropic conditions so that the oxidized layer is in conformity. At the same time, possibly in the same reactor, a less isotropic (and in practice highly isotropic) etching can be carried out so as to completely remove the oxidized layer only at the desired locations (i.e. out of the flank areas of the grid). According to certain aspects of embodiments of the invention, all the steps or at least some successive steps can be carried out within one and the same reactor. The use of plasma technology thus makes it possible to avoid manipulations. Note also that it is possible to obtain, when desired, spacers whose foot has a shrinkage, without having recourse to two series of phases of deposition and etching of nitride layers as in the state of the art. The invention is also relative, in embodiments, to a raised source / drain structure transistor in which a gate and source and drain regions are located above a layer of a semiconductor material, and which has spacers at the edges of the gate 30 configured to isolate the gate from the source and drain areas. This transistor is preferably such that the spacers have a single layer of a dielectric material, preferably silicon nitride. In addition or alternatively, the transistor may comprise at least partial coverage portions of the single layer of the spacers, preferably an oxide of the dielectric material of the single layer. According to a complementary or non-limiting alternative possibility, the source and drain zones are located in a single layer of a material, said single layer being situated above the layer of a semiconductor material. According to another nonlimiting possibility, the spacers comprise a foot zone above the layer of semiconductor material, the foot zone having a recess towards the side of the gate, so as to form a recess. Another aspect of the invention is a transistor, such as an MOS transistor, in which the gate spacers are partially covered with a surface layer of a material different from the material of the spacers, for example an oxide of the material of the spacers. Such a transistor can be obtained by the method of the invention. Another aspect of the invention relates to a method for producing a transistor in which the gate is located above a layer of a semiconductor material, said method comprising the production of spacers according to the production method. of spacers of the invention. It may include providing source and drain areas with epitaxial growth on the layer of semiconductor material. BRIEF DESCRIPTION OF THE FIGURES The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which: FIGS. 1 to 7 illustrate successive phases of producing two-level and source / drain spacers around a transistor gate, according to the state of the art, the two-level spacers having a shape such that their foot has a withdrawal to the grid. FIG. 8 shows a possible grid and substrate configuration from the method of the invention. Figures 9 to 14 show steps of the invention. FIG. 15 illustrates the single epitaxial step of the method of the invention during which the raised source and drain zones are made. FIG. 16a shows an undesired case of spacer foot shape which is observed after etching of the silicon nitride layer according to existing techniques. Figure 16b shows another unwanted case where the layer for epitaxial growth of the source and drain is attacked. FIG. 17 illustrates the absence of the defects mentioned in the two preceding figures when the method of the invention is used. The accompanying drawings are given by way of example and are not limiting of the invention. These drawings are schematic representations and are not necessarily at the scale of the practical application. In particular, the relative thicknesses of the layers and substrates are not representative of reality. DETAILED DESCRIPTION OF THE INVENTION Before going into the details of embodiment of the invention, particularly with reference to the drawings, non-limiting features which the invention may present individually or in any combination are briefly introduced hereinafter the formation of the surface layer comprises a modification of the material of only a portion of the thickness of the dielectric layer; The modification is an oxidation; the oxidation is carried out in a manner consistent with the flanks and the peripheral zone; the oxidation is carried out from a plasma; an oxygen plasma is used in which the energy of the ions is between 8 and 13 eV, preferably 10 eV; the formation of the surface layer comprises a deposit of a layer of material above the dielectric layer; The material of the layer of material above the dielectric layer is chosen from a material comprising carbon, an oxide such as silicon dioxide (SiO 2), a material containing Germanium and in particular silicon germanium or nitride; of Silicon Germanium, preferably with a germanium level of 15 to 40%. the partial removal of the surface layer is etching performed from a plasma; etching of the partial removal of the surface layer is an anisotropic etching configured to attack the surface layer at the peripheral zone while not attacking or attacking the surface layer at the gate less; the anisotropic etching is carried out with an argon or carbon tetrafluoride plasma in which the energy of the ions is between 8 and 13 eV, preferably 10 eV; the selective etching is operated from a plasma; the anisotropic etching is carried out, followed by selective etching in the same reactor; the selective etching is carried out wet; Selective etching is configured to partially etch the dielectric layer in a gate foot area below the residual portion toward the side of the gate so as to form a recess; the shrinkage has a height of between 5 and 30 nm, and preferably between 10 and 15 nm; The shrinkage has a width of between 5 and 10 nm and / or has a width less than that of the height of the shrinkage; the selective etching is configured to form a straight edge in the dielectric layer according to the thickness of the dielectric layer in alignment with the residual portion; the dielectric layer is made by a layer of nitride, preferably of silicon nitride; the dielectric layer is made of a low-k material of dielectric constant lower than that of the silicon nitride.
    [0008] It is pointed out that in the context of the present invention, the term "over", "overcomes" or "underlying" or their equivalents do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. by being either directly in contact with it or separated from it by another layer or another element. In the following description, the thicknesses are generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or a substrate on which the lower layer is disposed. Thus, the thicknesses are generally taken in a vertical direction in the figures shown. On the other hand, the thickness of a layer covering a flank of a pattern is taken in a direction perpendicular to this flank.
    [0009] In what follows, selective etching is understood to mean the etching removal of a given material while at least partly preserving, by the selectivity of the process employed, other materials. The term "surface layer" corresponds to a layer which is formed, in particular by modification of the underlying layer or by a deposit on this underlying layer, at the surface of the electronic device after the formation of the sub-layer. core. It is then partially removed to partially remove the underlying layer. The adjective "superficial" does not necessarily mean that the residual surface layer remains always on the surface of the device when the manufacture of the latter is finalized. It may for example be removed or covered. By "compliant" is meant a layer geometry which has the same thickness, with manufacturing tolerances, an identical thickness despite changes in layer direction, for example at the level of the grid pattern sidewalls.
    [0010] The word "dielectric" corresponds to a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator.
    [0011] The method for producing spacers according to the invention is illustrated in FIGS. 9 to 14. The method applies after the gates of the transistors have been formed, that is to say from a structure such as that illustrated in Figure 8 which is not different in this example from that of Figure 1 already described. The method of the invention can in fact potentially be implemented from any MOSFET transistor structure after the grid patterns have been defined by photolithography. In FIG. 8, used as a typical starting point example of an application of the method of the invention, there are thus the elements already described: the source and drain zones, 220 and 221, which are generally designated source / drain areas since they are very generally perfectly symmetrical and can play one or the other role depending on the electric polarizations that are applied to the transistor.
    [0012] The grid 200 conventionally consists of a stack of layers, a large part of which is always composed of polycrystalline silicon 201. The layers 203 and 204 constitute the gate oxide that most often comprises, in recent embodiments, a layer 204 of a material with a high relative permittivity called "high-k". The layer 202 is a hard mask for protecting at this stage of the stacking of the underlying gate layers. A conduction channel 205 between source and drain will be able to be formed if a suitable voltage is applied to the gate 100 developing a sufficient electric field through the dielectric layers 203 and 204. As has been seen, a currently used technique is to manufacture the integrated circuits from elaborate substrates SOI type. The layers of this type of substrate are found in the structure of FIG. That is to say: a thin superficial layer of monocrystalline silicon of Germanium or Silicon-Germanium 212 resting on a continuous insulating layer of oxide, called BOX, 211. The layer 210 constitutes the body of the SOI substrate.
    [0013] FIG. 9 illustrates the first step of the process of the invention during which the spacers will be produced in a single series of steps, in contrast to the traditional method, briefly described in the chapter on the state of the art, which It is necessary to implement two successive series of stages each comprising: the deposition of the material constituting the spacers, its etching and an epitaxial growth of the source / drain zones. As shown in FIG. 9, for producing the spacers in a single step, a single deposit of a layer 231 of a material such as silicon nitride (SiN) is carried out on a thickness corresponding to the total thickness 10 two spacers obtained with the standard method. Typically, a so-called "conformal" deposit is made over a thickness, for example ranging from 20 to 30 nm, preferably 25 nm. The deposit is consistent if it is done equally regardless of the orientation of the surfaces on which it is made. To obtain this result, the deposition is preferably carried out using a process known as PECVD, or an LPCVD process, acronym for English. "Lowpressure chemical vapor deposition". At the end of this step, as shown in FIG. 9, the deposited layer 231 is of substantially equal thickness on the sides of the grid patterns and on the horizontal portions, that is to say those parallel to the plane. of the substrate. As shown in FIG. 10, anisotropic etching of the layer 231 is carried out, that is to say a substantially vertical etching of the deposited material, etching which is therefore perpendicular to the plane of the substrate and which does not etch, or very little, the blanks of the grid patterns 206 and 207. This type of etching is advantageously carried out from a plasma in a capacitive coupling type (CCP) or inductively coupled (ICP) type etching reactor. preferably in a reactor of the latter type. This anisotropic etching is intended to reduce the thickness of the layer 231 in the peripheral zones surrounding the gate 200 to a value corresponding to the thickness (for example between 10 and 15 nm) of the first deposition of the material constituting the spacers. of the conventional process in which these are formed in two series of steps as discussed above. The conditions of such anisotropic etching are for example those for an inductively coupled reactor: pressure = 5 milli Torr; power of the source = 300 Watts; bias voltage = 65 volts; trifluoromethane flow rate (CHF3) = 30 sccm (cubic centimeters per minute); helium flow (He) = 220 sccm; substrate (e.g. electrostatic) carrier temperature = 110 ° C. Under these conditions, the etching rate of the silicon nitride, the standard material used for forming the spacers, is then of the order of 32 nm per minute. FIG. 11 illustrates the result of the next step in which surface oxidation 232 of the layer 231 of the spacer material is carried out. This operation is advantageously carried out isotropically from a plasma for example under the following conditions: pressure = 10 milli Torr; power of the source = 1000 Watts; oxygen flow rate (O 2) = 200 sccm; substrate holder temperature = 60 ° C. This oxidation is preferably produced in the same reactor as that of anisotropic etching. Alternatively, the layer 232 of oxide or of another material (such as silicon nitride Germanium or other material with Germanium, preferably with a Germanium content of 15 to 40%, or a carbonaceous material or SiO2 or other oxide) can be obtained by deposition. The thickness thus produced may be from 2 to 10 nm, preferably 7 to 20 nm. FIG. 12 shows the result of the next step at the end of which the oxidized layer 232 is left in place only on the flanks of the grid patterns. This result is obtained by means of a very anisotropic vertical etching operation called "breakthrough" which is practiced for example in an argon plasma (Ar) or carbon tetrafluoride (CF4) and which is serious essentially all oxidized surfaces parallel to the plane of the substrate. Leaving at least partly in place the oxidized surfaces not parallel to the substrate at the sidewalls 205, 206. FIG. 13 shows the result of the step of lateral etching of the parts 30 of the material forming the spacers which have been deoxidized at the same time. 'previous step. This etching is selective with respect to the underlying semiconductor layer 212 and also vis-à-vis the remaining oxidized layer 234 which are therefore not etched significantly during this operation.
    [0014] Optionally, it is therefore possible to obtain a lateral engraving at the foot of the spacers which reproduces the shapes obtained with the standard method as shown in FIG. 7. More generally, it is therefore possible to adjust a more or less marked shrinkage 233 as a function of the conditions of the engraving used or else not to have any withdrawal at all. Etching is here called lateral, in that it produces an attack substantially parallel to the substrate because of its selectivity. This etching is in fact preferably isotropic. As a result, the geometry of the shrinkage, in particular the flank of the shrinkage along the height h in FIG. 13, may be non-rectilinear. In practice, it may be in an arc.
    [0015] Lateral etching can be performed from plasma formed under the following conditions: pressure = 50 to 80 milli Torr; power of the source = 400 Watts; bias voltage = 250 volts; fluoromethane (CH3F) flow rate = 200 sccm; oxygen flow rate (O 2) = 200 sccm; helium flow (He) = 120 sccm; flow of silicon tetrachloride (SiCl4) = 5 sccm; substrate carrier temperature = 60 ° C. The bias voltage is preferentially pulsed at a frequency of 500 Hz with a duty cycle of 50%. Other pulsation conditions can be used: 200 Hz / 20%; 900 Hz / 90%; 200 Hz / 90%. The same reactor as before can be used. Lateral etching can also be done wet in a solution based on phosphoric acid (H 3 PO 4). In this case, the etching rate of silicon nitride, which is generally used for spacers, is 4 nm per minute. The temperature is for example between 80 ° C and 120 ° C and preferably 100 ° C. This chemistry has an infinite selectivity with respect to the oxide present on the residual portions 234 present on the sides of the spacers. It is also chosen selective with respect to the material of the layer 212. FIG. 14 shows a shape of the spacers 230 that can be obtained in practice with the method of the invention, the residual parts 234 having been removed, which It is not mandatory but can be done, especially during a cleaning step, particularly if the material of the parts 234 is an oxide sensitive to the cleaning solution. In fact, conventionally, prior to the epitaxial operation, the surface of the layer 212 from which the epitaxial growth is to be made is preferably wet cleaned. Cleaning is preferably carried out using a solution based on hydrofluoric acid (HF), for example diluted to 0.5%, for 30 seconds. This cleaning is intended to remove the polymers and the native oxide layer on the surface of the semiconductor 5 which is silicon (Si) or a compound of silicon and germanium (SiGe). In another embodiment, the portions 234 are held in place. Figure 15 illustrates the selective epitaxial growth step 235 of the source and drain zones that is performed next. As has been seen this operation is carried out only once with the process of the invention whereas it must be repeated a second time when using the standard method of forming the spacers. An epitaxial layer 235 of a thickness, for example equivalent to that obtained with the standard method, is grown at the end of the second series of steps of formation of the spacers. For the formation of the source and drain zones, in-situ doping of these zones can be carried out, that is to say in the epitaxial reactor itself, by introducing therein, in gaseous form, the doping species required, such as the boron (P type doping) or arsenic (N type doping). Optionally, if in-situ doping is not used, it will be possible, after formation of the epitaxial layer 20, to implant the doping species in an implanter. In an alternative embodiment of the invention, the material constituting the spacers may advantageously be a material with a lower relative permittivity (Low-k) than the silicon nitride which is conventionally used in order to reduce the parasitic capacitances of the transistor ( between drain / source on the one hand and the grid on the other hand). FIG. 16a illustrates a problem that commonly occurs with the standard method of making spacers where it is difficult to control the etching of the first spacer without damaging the thin superficial semiconductor layer 212 of the substrate (such damage is illustrated in FIG. 16b). In wanting to avoid damaging this layer, "feet" 134 are often formed in a very undesirable manner at the bottom of the first spacers. Another problem mentioned above of the standard method of forming the spacers where, when etching too much of the first spacers, damage occurs, as in FIG. 16b, the thin layer 212 of semiconductor which makes it impossible to then proceed to a faultless epitaxy of the source and drain zones. Thus, the standard method involves either a bad geometry of the spacer's foot, or a deterioration of the layer of the semiconductor material serving as the basis for epitaxy. The method of the invention makes it possible to overcome these problems. As shown in FIG. 17, there is no longer a formation of feet because the etching plasma parameters can be adjusted, notably the etching time, without damaging the semiconductor layer 212, a layer from which one is going to go. ability to epitaxize the source and drain areas without defects.
    权利要求:
    Claims (23)
    [0001]
    REVENDICATIONS1. A method of making spacers (230) at flanks (206,207) of a transistor gate (200) in which the gate is located above a layer of a semiconductor material (212), the process comprising successively the following steps: - formation of a dielectric layer (231) which covers the gate (200) and at least one peripheral zone (220, 221) of the layer of semiconductor material (212) surrounding the gate ( 200); forming a surface layer (232) covering the dielectric layer (231); partially etching the surface layer (232) configured to completely remove the surface layer (232) at the peripheral zone (220, 221) while preserving a residual portion (234) of the surface layer (232) at the level of flanks (206,207); etching the dielectric layer (231) selectively with respect to the residual portion (234) of the surface layer (232) and with respect to the layer of semiconductor material (212).
    [0002]
    The method of claim 1 wherein forming the surface layer (232) comprises modifying the material of only a portion of the thickness of the dielectric layer (231).
    [0003]
    The process of claim 2 wherein the modification is an oxidation.
    [0004]
    4. The method of claim 3 wherein the oxidation is carried out in a manner consistent with the flanks (206,207) and the peripheral area (220, 221).
    [0005]
    5. Method according to one of claims 3 or 4 wherein the oxidation is carried out from a plasma. 3025938 17
    [0006]
    6. The method of claim 5 wherein an oxygen plasma is used in which the energy of the ions is between 8 and 13 eV, preferably 10 eV.
    [0007]
    The method of claim 1 wherein the formation of the surface layer (232) comprises depositing a layer of material above the dielectric layer (231).
    [0008]
    The method of claim 7 wherein the material of the material layer above the dielectric layer (231) is selected from: a material comprising carbon, silicon dioxide (SiO 2), a material containing germanium
    [0009]
    9. Method according to one of the preceding claims wherein the partial etching of the surface layer (232) is etching operated from a plasma, and wherein the partial etching of the surface layer (232) is an anisotropic etching configured to etch the surface layer (232) at the peripheral area (220, 221) while not attacking or otherwise attacking the surface layer (232) at the gate (200).
    [0010]
    10. The method of claim 9 wherein the anisotropic etching is performed with an argon plasma or carbon tetrafluoride in which the energy of the ions is between 8 and 13 eV, preferably 10 eV. 20
    [0011]
    11. Method according to one of the preceding claims wherein the etching of the dielectric layer (231) is operated from a plasma.
    [0012]
    12. Method according to the preceding claim in combination with one of claims 9 or 10 wherein the anisotropic etching is carried out and the etching of the dielectric layer (231) in the same reactor. 25
    [0013]
    13. Method according to one of claims 1 to 10 wherein the etching of the dielectric layer (231) is operated by wet.
    [0014]
    The method of one of the preceding claims wherein the etching of the dielectric layer (231) is configured to partially etch the dielectric layer (231) in a gate foot area below the residual portion (234) in direction of the side of the gate (206,207), so as to form a withdrawal (233).
    [0015]
    15. The method of claim 14 wherein the shrinkage (233) has a height of between 5 and 30 nm, and preferably between 10 and 15 nm. 3025938 18
    [0016]
    The method of claim 14 or 15 wherein the shrinkage (233) has a width of between 5 and 10 nm and / or has a width less than that of the height of the shrinkage.
    [0017]
    The method of one of claims 1 to 13 wherein the etching of the dielectric layer (231) is configured to form a straight edge in the dielectric layer (231) according to the thickness of said dielectric layer in alignment with the residual part (234).
    [0018]
    18. A method of producing a transistor in which the gate is situated above a layer of a semiconductor material (212), said method comprising the production of spacers (230) according to the method according to the invention. any of the preceding claims.
    [0019]
    19. Method according to the preceding claim, comprising producing source and drain zones with epitaxial growth on the layer of semiconductor material (212). 15
    [0020]
    A raised source / drain structure transistor in which a gate (200) and source and drain regions are located above a layer of a semiconductor material (212), and which has spacers ( 230) at the sidewalls of the gate (200) configured to isolate the gate (200) from the source and drain regions, characterized in that the spacers (230) have a single layer of a dielectric material, preferably silicon nitride.
    [0021]
    21. Transistor according to the preceding claim, comprising portions (234) of at least partial coverage of the single layer of the spacers (230), preferably an oxide of the dielectric material of the single layer.
    [0022]
    22. Transistor according to one of the two preceding claims, wherein the source and drain zones are located in a single layer (235) of a material, said single layer (235) being located above the layer of a semiconductor material (212). 30
    [0023]
    23. Transistor according to one of the three preceding claims wherein the spacers (230) comprise a foot zone above the layer of semiconductor material (212), the foot zone having a withdrawal (233). in the direction of the side of the grid (206, 207), so as to form a recess.
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    FR3080486A1|2019-10-25|METHOD FOR FORMING A MICROELECTRONIC DEVICE
    FR3046876A1|2017-07-21|CONSUMPTION OF A TRANSISTOR CHANNEL BY SACRIFICIAL OXIDATION
    FR3046875A1|2017-07-21|PROCESS FOR PRODUCING A TRANSISTOR
    EP3671815A1|2020-06-24|Method for etching a three-dimensional dielectric layer
    FR3047352A1|2017-08-04|METHOD FOR MANUFACTURING A DOPANT TRANSISTOR LOCATED AT THE GRIT APLOMB
    FR3098978A1|2021-01-22|manufacturing process of transistors
    FR3098981A1|2021-01-22|manufacturing process of transistors
    EP3107124B1|2018-04-04|Method for forming spacers of a transistor gate
    同族专利:
    公开号 | 公开日
    EP2999001A3|2016-04-13|
    FR3025938B1|2018-05-25|
    US9543409B2|2017-01-10|
    US20160079388A1|2016-03-17|
    EP2999001A2|2016-03-23|
    EP2999001B1|2019-09-04|
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    KR101025740B1|2003-12-19|2011-04-04|주식회사 하이닉스반도체|Method for fabricating transistor having deposited junction|FR3098981A1|2019-07-18|2021-01-22|Commissariat A L'energie Atomique Et Aux Energies Alternatives|manufacturing process of transistors|
    FR3098978A1|2019-07-18|2021-01-22|Commissariat A L'energie Atomique Et Aux Energies Alternatives|manufacturing process of transistors|US6232641B1|1998-05-29|2001-05-15|Kabushiki Kaisha Toshiba|Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor|
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    法律状态:
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    2016-03-18| PLSC| Search report ready|Effective date: 20160318 |
    2016-09-29| PLFP| Fee payment|Year of fee payment: 3 |
    2017-09-28| PLFP| Fee payment|Year of fee payment: 4 |
    2018-09-28| PLFP| Fee payment|Year of fee payment: 5 |
    2019-09-30| PLFP| Fee payment|Year of fee payment: 6 |
    2021-06-11| ST| Notification of lapse|Effective date: 20210506 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1458759A|FR3025938B1|2014-09-17|2014-09-17|REALIZING SPACERS AT THE FLANK LEVEL OF A TRANSISTOR GRID|
    FR1458759|2014-09-17|FR1458759A| FR3025938B1|2014-09-17|2014-09-17|REALIZING SPACERS AT THE FLANK LEVEL OF A TRANSISTOR GRID|
    EP15184982.5A| EP2999001B1|2014-09-17|2015-09-14|Production of spacers at the edges of a transistor gate|
    US14/855,834| US9543409B2|2014-09-17|2015-09-16|Production of spacers at flanks of a transistor gate|
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